Recently I heard a talk by a guy from Oracle designing Sparc CPUs. IIRC, he said that while they could potentially put bigger caches on their CPUs, for their test-cases it wasn't that much of a benefit above their chosen size.
Another interesting note from that talk was that they had spent a large amount of time making an 8 socket architecture with quick-connect paths between all pairs of sockets for memory transport. Unfortunately that was not as important as believed either, since the programs that typically benefit from 8 CPUs normally have good memory properties anyway.
Not sure if either data-points are true, but interesting nonetheless.
Another interesting note from that talk was that they had spent a large amount of time making an 8 socket architecture with quick-connect paths between all pairs of sockets for memory transport. Unfortunately that was not as important as believed either, since the programs that typically benefit from 8 CPUs normally have good memory properties anyway.
Not sure if either data-points are true, but interesting nonetheless.