Until Intel's Ice Lake server processors introduced in 2019, x86-64 essentially was a 48-bit address architecture: addresses are stored in 64-bit registers, but were only valid if the top two bytes were sign-extended from the last bit of the 48-bit address. Now they support 57 bit addressing.
True. However what I had in mind there was something along the lines of 48-bit integer and fp arithmetic as the "native" size with 96-bit as the much more limited extended form that 128-bit currently fulfills for x86. For the address space regular 48-bit pointers would address the needs of typical applications.
Extended 96-bit pointers could address the (rather exotic) needs of things such as distributed HPC workloads, flat byte addressable petabyte and larger filesystems, etc. Explicitly segmented memory would also (I assume) be nice for things like peripheral DMA, NUMA nodes, and HPC clusters. Interpreters would certainly welcome space for additional pointer tag bits in a fast, natively supported format.
Given the existence of things like RIP-relative addressing and the insane complexity of current MMUs such a scheme seems on its face quite reasonable to me. I don't understand (presumably my own lack of knowledge) why 64-bit was selected. As you point out addresses themselves were 48-bit in practice until quite recently.
