Quick question: under specs for the M0+ where they say, >Enhanced Instructio... | Hacker News

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		zxcvvcxz on March 13, 2012 \| parent \| context \| favorite \| on: Arm unveils 1mm x 1mm 32bit chip: "years of batter... Quick question: under specs for the M0+ where they say, >Enhanced Instructions >Hardware single-cycle (32x32) multiply option Does that mean their hardware can multiply 32-bit by 32-bit numbers in a single clock cycle?? I took a computer organization course where I implemented a simple hardware multiplier and it took a lot more cycles than that, so I was curious.

omgtehlion on March 13, 2012 | [–]

You can create HW multiplier using only NOR+AND elements. It will consume a lot of silicon, but will work fast enough.

BTW, most FPGAs have HW multiplier prebuilt block, because you will loose lots of flip-flops or LUTs (or both) implementing one yourself.

abecedarius on March 13, 2012 | [–]

Probably means throughput, not latency.

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