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torginus
on Dec 27, 2020
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The Genius of RISC-V Microprocessors
Since ARM has plenty of space in a 32 bit instruction, both the shift and the add are baked into the ldr instruction.
duskwuff
on Dec 28, 2020
[–]
Even in Cortex-M, most array accesses are two instructions (lsls+ldr), as the ldr includes a "free" register+register add. For example, given an index in r0 and an array base address in r3:
lsls r0, r0, #2 ldr r0, [r0, r3]
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