But your actual performance is really more along the lines of clock speed times instructions per cycle. For example, a 5.0 GHz CPU that only achieves 1 instruction per cycle only does half the work of a 2.0 GHz CPU that achieves 5 instructions per cycle.
Some factors that deeply influence achievable IPC include at least (1) the cache sizes and layout, number of load/store pipes, prefetching relevance and timeliness, and overall memory system design, (2) the kinds, number, and capabilities of the execution units and the quality of the scheduler for these units, and (3) the front-end's ability to correctly predict branches, speed of recovery from mispredicts, and general ability to keep feeding the back-end of the machine.
Beyond that you really need to multiply in the amount of actual work done per instruction. A factor here is the instruction set and the ability of the compiler to utilize it to effectively. For instance, a "single" vector instruction may do an amount of computation similar to 4, 8, 16, or even 32 conventional instructions. Code that uses these instructions may get a massive speedup on CPUs that have enough execution resources to execute many or all "lanes" of the instruction in parallel...
But your actual performance is really more along the lines of clock speed times instructions per cycle. For example, a 5.0 GHz CPU that only achieves 1 instruction per cycle only does half the work of a 2.0 GHz CPU that achieves 5 instructions per cycle.
Some factors that deeply influence achievable IPC include at least (1) the cache sizes and layout, number of load/store pipes, prefetching relevance and timeliness, and overall memory system design, (2) the kinds, number, and capabilities of the execution units and the quality of the scheduler for these units, and (3) the front-end's ability to correctly predict branches, speed of recovery from mispredicts, and general ability to keep feeding the back-end of the machine.
Beyond that you really need to multiply in the amount of actual work done per instruction. A factor here is the instruction set and the ability of the compiler to utilize it to effectively. For instance, a "single" vector instruction may do an amount of computation similar to 4, 8, 16, or even 32 conventional instructions. Code that uses these instructions may get a massive speedup on CPUs that have enough execution resources to execute many or all "lanes" of the instruction in parallel...